Integrated circuits with copper interconnects are devices well known in the art. Such devices include a semiconductor substrate having circuits formed therein by diffusion. Overlying the substrate is usually one or more copper interconnect layers separated by insulating layers. The copper interconnect layers are configured to distribute external signals and power and ground about the integrated circuit and are connected to the integrated circuit by vias in the insulating layer or layers.
While such devices are used widely, it has been found that as circuit density increases, power delivery to the integrated circuits becomes increasingly difficult. This is at least partly due to die size, operating frequencies, and device leakage.
Integrated circuits with copper interconnects also can suffer from delamination. This delamination may be due to a mismatch of expansion coefficients between the package overmold compound used in the devices and the metal interconnects.
In the past, the above deficiencies have been addressed by the provision of wider metal interconnect tracks. This has also required additional power and ground cells to accommodate the wider metal interconnect tracks. Further, additional metal interconnect layers have been included in the devices. Still further, different molding compounds have been adapted for packaging the devices. Unfortunately, these measures are generally more expensive to employ.
In integrated circuits employing copper interconnects, connectivity to the package is accomplished by transition vias to top surface aluminum bond pads. The bonding pads are used as bonding sites for wire bonding or a solder bump redistribution layer.
The present invention provides an improved integrated circuit employing copper interconnects. The integrated circuit of the present invention provides protection against to copper interconnect delamination. It further provides power delivery to the devices with reduced resistance and increased reliability at reduced costs.